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Chapter 3. Technical description of the hardware architecture 43

3.1 POWER6 processor

The POWER6 processor capitalizes on the enhancements brought by the

POWER5 processor.

Two of the enhancements of the POWER6 processor are the ability to do

processor instruction retry and alternate processor recovery. This significantly

reduces exposure to both hard (logic) and soft (transient) errors in the processor

core.

򐂰 Processor instruction retry

Soft failures in the processor core are transient errors. When an error is

encountered in the core, the POWER6 processor will first automatically retry

the instruction. If the source of the error was truly transient, the instruction will

succeed and the system will continue as before. On predecessor IBM

systems, this error would have caused a checkstop.

򐂰 Alternate processor retry

Hard failures are more difficult, being true logical errors that are replicated

each time the instruction is repeated. Retrying the instruction will not help in

this situation because the instruction will continue to fail. Systems with

POWER6 processors introduce the ability to extract the failing instruction from

the faulty core and retry it elsewhere in the system, after which the failing core

is dynamically deconfigured and called out for replacement. The entire

process is transparent to the partition owning the failing instruction. Systems

with POWER6 processors are designed to avoid what would have been a full

system outage.

򐂰 POWER6 single processor checkstopping

Another major advancement in POWER6 processors is single processor

checkstopping. A processor checkstop would result in a system checkstop. A

new feature in the BladeCenter JS23 Express server is the ability to contain

most processor checkstops to the partition that was using the processor at

the time. This significantly reduces the probability of any one processor

affecting total system availability.

򐂰 POWER6 cache availability

In the event that an uncorrectable error occurs in L2 cache, the system will be

able to dynamically remove the offending line of cache without requiring a

reboot. In addition, POWER6 utilizes an L1/L2 cache design and a

write-through cache policy on all levels, helping to ensure that data is written

to main memory as soon as possible. It can also make use of an additional

32MB chip-shared L3 cache.

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